Driven by economic pressures which manifest themselves as Moore’s law, over the past 35-40 years the transistor gate length has shrunk by a factor of 100 (from 3 micron to 30 nm), wafer size has increased by a factor of 4 (from 75 to 300 mm), the gate stack materials have changed (SiO₂ to HfOₓ gate) and geometry have changed as well (from planar to tri-gate). At the same time, the number of yielding transistors on a chip has gone from 30,000 into billions of billions.

How has the plasma etch chamber, chemistry, parameters, control changed during this time span to help produce billions of identical and functioning on a chip? And what do we expect of plasma etch equipment and process when transistor dimensional scaling stops, and we start stacking transistors vertically?

As a test case, this presentation will explore the evolution of the transistor gate and the gate etch equipment and process: how etch tools, chemistry, process uniformity and variability requirements, process control have evolved to faithfully etch billions of features to yield a functioning chip.